发明名称 STRING REDUNDANCY ARCHITECTURE FOR READ/WRITE MEMORY
摘要 PURPOSE: To relate one redundant column of a pair of redundant array blocks to one of input/output terminals by substituting one column in array halves with this redundant column. CONSTITUTION: A redundant array block 30a has 8 redundant columns 350 to 357 , and each redundant column has memory cells which can be selected in accordance with the row address which corresponds to the same row address for selection of memory cells in the main array blocks 100 to 107 and is generated from a row decoder 24a. Similarly, a redundant array block 30b has 8 redundant columns 358 to 3515 and each redundant column has memory cells which can be selected based on the same row address for selection of memory cells in blocks 108 to 1015 . Each of redundant columns 35 in blocks 30a and 30b can be substituted for one column of the main array block 10 of array halves and can be related to one of input/output terminals DQ.
申请公布号 JPH06236700(A) 申请公布日期 1994.08.23
申请号 JP19930014568 申请日期 1993.02.01
申请人 S G S THOMSON MICROELECTRON INC 发明人 DEIBITSUDO SHII MAKUKURUUA;NARASHINHAN IENGAA
分类号 G11C11/401;G11C29/00;G11C29/04;(IPC1-7):G11C29/00 主分类号 G11C11/401
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