发明名称 |
Low voltage, cascoded NTL based BiCMOS circuit |
摘要 |
A BiCMOS circuit including an NFET transistor connected as a diode is disclosed. The NFET transistor provides a threshold level for sourcing current. A PFET transistor and a clamping diode are connected in parallel to serve as a current path to the base of a bipolar emitter follower transistor. The emitter follower transistor and an NFET transistor act as pull-up and pull-down devices at the output stage. The NFET-diode turns off the current in the logic network as well as in the output buffer when the inputs are at a low logic level. As a result, the power consumed by this NTL based BiCMOS circuit is lower compared to that of an ECL based BiCMOS circuit. Also the drawbacks of a conventional NTL circuit, low noise immunity and signal degradation, are eliminated because the NFET-diode serves as a reference level for input signals. An additional embodiment wherein CMOS logic is cascoded with the existing bipolar logic to allow a higher logic function is also disclosed. The circuit of this invention can provide a single-phase output which is compatible with a low-voltage ECL/BiCMOS signal.
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申请公布号 |
US5341042(A) |
申请公布日期 |
1994.08.23 |
申请号 |
US19920926436 |
申请日期 |
1992.08.10 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CHEN, CHIH-LIANG |
分类号 |
H03K19/08;H03K19/086;H03K19/0944;(IPC1-7):H03K17/16;H03K19/094 |
主分类号 |
H03K19/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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