发明名称 |
Semiconductor device and manufacturing method thereof |
摘要 |
A gate electrode of a P-channel MOS transistor and a gate electrode of an N-channel MOS transistor which constitute a logic section, a gate electrode of an N-channel MOS transistor and a capacitor electrode which constitute a memory cell section are formed by patterning a first layer of polysilicon, so that the semiconductor device can be manufactured in a considerably simplified process as an SRAM, while taking advantage of the large capacity of a DRAM thereby to improve the yield.
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申请公布号 |
US5341324(A) |
申请公布日期 |
1994.08.23 |
申请号 |
US19920953699 |
申请日期 |
1992.09.30 |
申请人 |
SUMITOMO METAL INDUSTRIES, LTD. |
发明人 |
MATSUMOTO, TOSHIYUKI;INADA, HIROFUMI;NITTAYA, HIROSHI;KATO, MASAHIRO |
分类号 |
G02F1/1345;G02F1/136;G02F1/1368;H01L21/822;H01L21/8234;H01L21/8244;H01L27/04;H01L27/06;H01L27/10;H01L27/11;(IPC1-7):G11C11/24 |
主分类号 |
G02F1/1345 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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