| 摘要 |
PURPOSE: To reduce the load for a host computer by successively feeding image display data for respective image blocks soon after a overview code into an arithmetic processing circuit with the host computer. CONSTITUTION: After receiving an overview instruction word U from e.g. the host computer, an overview instruction library file 31 is searched with a receiving and processing means 4, a series of instruction processing words (V1 , V2 ,..., Vn ) for respective image blocks are formed, based on the overview instruction word U and an overview instruction library M, and fed to an image change control means 5 in which control signals S for an image display part 6 are formed, based on information included in a process recognition word W called out of a process recognition word file 32 and information included in instruction processing words (V1 , V2 ,..., Vn ). By this way, a series of image display data are merely transmitted to the receiving and processing means 4 soon after the overview code X with the host computer, whereby the load is reduced, compared with a conventional device. |
