| 摘要 |
PURPOSE:To process multilevel logical data asynchronously in a high speed by inserting control information to a data signal itself of multilevel logic. CONSTITUTION:A counter circuit 4 sets optionally a width of parallel outputs and is a down counter having three-bit initial value inputs i1, i2, and i3. Ternary logic is used as multilevel logic, and the logic where data signals I1 and I2 are ''0'' together is allowed to correspond to logical ''0'', and the logic where these data signals are ''1'' together is allowed to correspond to logical ''1'', and the logic where one of them is ''0'' (or ''1'') and the other is ''1'' (or ''0'') is allowed to Nil. Nil of ternary logic is used as control information and is inserted between data to discriminate individual data signals. That is, properties that data signals I1 and I2 have the same value ''0'' or ''1'' during the period of data logical ''0'' and ''1'' of ternary logic and thay have different values during the period of Nil are utilized. |
