| 摘要 |
PURPOSE:To contrive the increase of integration and improve the characteristics by a method wherein the interval between capacitor holes is brought close into the limitation in resolution of an mask aligner with a structure that the conventional oxide film for element isolation has been removed. CONSTITUTION:After a P<+> layer 12 and an SiN film 31 are successively provided on a P type substrate 11, holes 81 and 82 are bored. A poly Si layer 32 doped with As is provided; thereafter, an N<+> layer 22 is provided around the holes 81 and 82 by heating. After exfoliation of the film 31 and the layer 32, the N<+> layer 22 is extended onto the P<+> layer 12 by selective As ion implantation. Afterward, an SiO2 film 32 is formed, and the first poly Si layer 5 is formed over the whole surface. After selective removal of this layer 5, a P<-> layer 13 is formed by As or P ion implantation. The top of the P<-> layer 13 and that of the layer 5 are formed into a gate oxide film 4 by oxidation. After the second poly Si layer 6 is formed thereon, source-drain diffusion 21 is carried out. A thick SiO2 film 10 is formed over the whole surface, and a contact 21 is opened, and an Al wiring 7 is formed; finally, a PSG film 33 for protection is formed. |
