发明名称 |
Self-aligned contacts with gate overlapped lightly doped drain (goldd) structure |
摘要 |
In a method for producing a transistor with an overlapping gate region, a gate region is placed on a substrate between two source/drain regions. Spacers are placed around the gate region. The spacers are formed of dielectric material. A thin layer of polysilicon is deposited over the two source/drain regions and over electrically insulating regions adjacent to the two source/drain regions. Portions of the thin layer of polysilicon are oxidized to electrically isolate the two source/drain regions. A metal-silicide layer is formed on the portions of the thin layer of polysilicon which are not oxidized. The metal-silicide layer is connected to a metal layer. The electrical contact of the metal-silicide layer and the metal layer is over an electrically insulating layer.
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申请公布号 |
US5340761(A) |
申请公布日期 |
1994.08.23 |
申请号 |
US19910786321 |
申请日期 |
1991.10.31 |
申请人 |
VLSI TECHNOLOGY, INC. |
发明人 |
LOH, YING T.;WANG, CHUNG S. |
分类号 |
H01L21/285;H01L21/336;(IPC1-7):H01L21/336;H01L21/28 |
主分类号 |
H01L21/285 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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