| 摘要 |
<p>PURPOSE:To provide a designing method wherein it reduces the occupied area of an I/O cell for a logic LSI and it makes the multi-pin structure of an LSI package easy. CONSTITUTION:When I/O cells SL1, SL2,... constituting a buffer circuit for input/output on a semiconductor chip 1 are arranged and installed, a plurality of first basic cells 101, 102,... and second basic cells 201, 202,... are lined up and installed in prescribed regions on the chip. According to the number of transistors required to constitute desired I/O cells, one or two or more basic cells are selected from the plurality of basic cells, and I/O cell regions S1, S2,... are partitioned. By using elements inside the partitioned I/O cell regions S1, S2,..., a wiring pattern forming the I/O cells is designed. Bonding pads 2, 2,..., are formed on the chip 1 at a definite ratio with reference to the plurality of first and second basic cells, and a multi-pin structure can be achieved.</p> |
