| 摘要 |
PURPOSE:To prevent the storage data of a volatile memory from being deleted without using a battery back-up when a power source is interrupted. CONSTITUTION:The interrupting period of a direct current power source output from a power source 26 for cache when interruption occurs, is delayed by (the discharge action of) a capacitor 263 connected with a smoothing circuit 262 in the power source 26 in parallel. At that time, the supply of the direct current power source from the power source 26 to a cache RAM 23, EEPROM 24, and data saving/restoration control circuit 25 is continued regardless of the occurrence of interruption. Also, at the time of the interruption (direct current power source interruption), a power source interruption signal 27 is outputted from the power source 26. Then, the data saving/restoration control circuit 25 operates data saving from the cache RAM 23 to the EEPROM 24. On the other hand, at the time of restoration from the power source interruption, the data saving/restoration control circuit 25 waits for the end of the change of the capacitor 263, and operates data restoration from the EEPROM 24 to the cache RAM 23. |
