| 摘要 |
PURPOSE:To simply avoid a clock skew in the case of configuring a multi-bit shift key by providing a flip-flop(FF) circuit including input and output terminals for a data signal and a clock signal input and output terminals. CONSTITUTION:The circuit is provided with a clock signal output terminal 10 outputting a clock signal received by a clock signal input terminal 9. Furthermore, input and output terminals 1,8 are arranged so as to propagate the clock signal in an opposite direction to the propagation direction of a data signal. When plural FF circuits are connected in the propagation direction (shown by an arrows) of the data and clock signals, the data signal is propagated from a pre-stage FF circuit to post-stage FF circuits and the clock signal is propagated from a post-stage FF circuit to pre-stage FF circuits. Thus, the post-stage FF circuits receive a fetch clock signal for the data signal shifted by the pre-stage FF circuits. Thus, the relative positional relation on a time axis between the data signal and the clock signal is always warranted to avoid clock skew. |
