| 摘要 |
PURPOSE:To output decision point data without slip of a recovered clock signal even when a fixed clock sampling demodulator uses the consecutive mode by operating an interpolation circuit for the same period as that of a symbol clock of a reception signal. CONSTITUTION:A clock phase detector 50 inputs an output signal of a nonlinear processing circuit 8 and a fixed clock signal to calculate an estimated phase difference between the symbol clock of the reception signal and the output of a phase generator and outputs the output of the generator. A decision point detector 51 generates an interpolation start pulse and decision point phase information from the output signal of the detector 50. A shift register 52 is operated by a signal from a fixed oscillator 3 to store an A/D conversion value of Ich, Qch signals subjected to quasi-synchronization detection. Furthermore, an interpolation circuit 53 inputs the timing of a decision point being the output of a clock phase estimate circuit 102 and phase information and fetches the A/D conversion value in the inside of the register 52 and obtains the decision point data of each symbol by the interpolation calculation. |
