| 摘要 |
PURPOSE:To shorten interpolation processing time by taking out plural pieces of image data required for interpolation from plural frame memories simultaneously and in parallel. CONSTITUTION:Decoders 20-23 of the same number of pieces as the number of pieces of image data required for interpolation are provided, and a two-dimensional address is generated at an address generation circuit 10 according to an interpolation instruction from the outside, and it is added on the decoders 20-23, and conversion addresses in which the two-dimensional address is converted by a conversion rule supplied in advance by the decoders 20-23 are outputted, and those conversion addresses are added to frame memories 30-33 of the same number of pieces as the number of pieces of decoders 20-23 storing image data in advance, and corresponding image data are outputted from the frame memories 30-33 to a data re-arranging circuit 40, and the re-arrangement of the image data is performed, and the output from the circuit is added to an interpolation arithmetic circuit 41, and the linear interpolation of the image data is performed by the two-dimensional address to be added separately and the image data, then, the result is outputted to the outside. |
