发明名称 OPERATION PROCESSOR
摘要 PURPOSE:To prevent the propagation of a carry value in internal addition/ subtraction, to simplify circuit constitution and to easily perform mounting to an LSI chip by performing conversion to a digit number with a code by performing subtraction by a subtraction means. CONSTITUTION:An intermediate partial product generator 110 obtains the product of a multiplicand and the digit of a multiplier recorded by a multiplier recorder 100 and generates an intermediate partial product. A redundant subtractor 120 subtracts the adjacent odd-numbered, that is, (2k+1)-th partial product generated at the intermediate partial product generator 110 from the even-numbered, that is, (2k)-th partial product generated at the intermediate partial product generator 110 and outputs the difference in the form of redundant binary numbers for which respective digits are any values of {-1, 0, +1.} A redundant adder 130 constitutes an addition tree and performs addition in the redundant binary system of general redundant binary numbers. A redundant binary/binary converter 140 converts the redundant binary number obtained as the product to a binary number.
申请公布号 JPH06230933(A) 申请公布日期 1994.08.19
申请号 JP19930112842 申请日期 1993.05.14
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 NISHIYAMA TAMOTSU;KUNINOBU SHIGERO
分类号 G06F7/49;G06F7/52;G06F7/53;G06F7/533 主分类号 G06F7/49
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