发明名称 CLOCK REPRODUCING CIRCUIT
摘要 PURPOSE:To reproduce a source clock when a cell is abandoned or delayed. CONSTITUTION:An SAR header is separated from a received cell by an SAR header separation part 101, and a sequence number 104 and frequency difference information 105 are detected from the separated, SAR header 102 by a sequence number/frequency difference information detection part 103. A sequence number monitor part 106 monitors the sequence number and detects the cell abandonment or the cell delay, and concerning the omission and delay frequency difference information the average value of preceding frequency difference information calculated at a frequency difference information operation processing part 114 recorded in a memory 110 is outputted by a frequency difference information managing part 108, and a source clock 113 is reproduced by using the frequency difference information average value and a network clock 112 by a clock reproducing part 111.
申请公布号 JPH06232895(A) 申请公布日期 1994.08.19
申请号 JP19930015204 申请日期 1993.02.02
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SAKAI TAKAHISA;NISHIOKA MINORU;MURASE KOICHI;KITAO MITSURU
分类号 H04L7/00;H04L7/08 主分类号 H04L7/00
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