| 摘要 |
<p>The appts. includes a reference frequency for providing a number of reference frequency signals having predetermined reference frequencies F1, F2 and F3. A first frequency shifted is coupled to the reference frequency device, and shifts the frequency of the first signal at frequency F1. A first phase locked loop, also coupled to the reference frequency device, receives the frequency shifted reference frequency signal at F1' and the second reference frequency signal at F2, and provides an intermediate output signal at frequency FI in response. A second frequency shifter is coupled to the first PLL for shifting the frequency of the intermediate frequency signal FI to provide a frequency shifted intermediate frequency signal FI'. A second PLL is coupled to the reference frequency device and to the second frequency shifter for receiving the third reference frequency signal F3 and the shifted intermediate signal FI', and provides an output signal of the frequency synthesiser at frequency FO.</p> |
