| 摘要 |
<p>PURPOSE:To eliminate the influence of jitter caused by reception side noise generated in the case of synchronizing transmission/reception timing with the timing of the opposite side station or high-order network of burst transmission/ reception, to make the circuit into an IC and to reduce power consumption at the time of TDMA mobile communication for performing communication through a base station. CONSTITUTION:This circuit is provided with a clock generating circuit 1 for generating a clock at the N-fold frequency of a processing clock to generate the transmission/reception timing, a frequency dividing phase control circuit 2 for outputting a frequency divided phase phi for which one of totally N pieces of outputs dividing the frequency and delaying it just for a 1/N cycle later is selected, transmission/reception timing generation circuit 6 for outputting a desired transmission/reception timing output TO and a gate timing signal GT. Then, phase difference between reception frame timing FT and a frame clock FC from a frequency dividing circuit 3 is detected and stored, and the frequency divided phase phi corresponding to a phase difference output 5 is selected when the GT is turned on.</p> |
