发明名称 CLOCK SIGNAL GENERATING CIRCUIT
摘要 <p>PURPOSE:To equivalently transmit a clock signal in which a clock skew between respective units is small and stable, to each unit without being affected by the scale of a circuit by distributing the clock signal inputted from the, outside by using a clock distributing means in an LSI. CONSTITUTION:A clock signal generating means 1 generates a clock signal 102 obtained by amplifying a clock signal 101 corresponding to the input of the clock signal 101. Next, a clock distributing means 2 in a semiconductor integrated circuit generates clock signals 103-1-103-n obtained by distributing the clock signal 102 corresponding to the input of the clock signal 102, and transmits those clocks to clock skew control means 3-1-3-n. Moreover, the clock skew control means 3-1-3-n generate clock signal groups 104-1-104-n obtained by adjusting the clock skew corresponding to the input of the clock signals 103-1-103-n, and transmits them to each unit.</p>
申请公布号 JPH06222856(A) 申请公布日期 1994.08.12
申请号 JP19930009637 申请日期 1993.01.25
申请人 NEC CORP 发明人 TAKAYAMA OSAMU
分类号 G06F1/04;G06F1/10;(IPC1-7):G06F1/10 主分类号 G06F1/04
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