| 摘要 |
The Y-decoder layout area is decreased and the Y address path delay is shorter by using the column I/O structure of a memory device. The structure includes a duplicated I/O line (51) for receiving data from a duplicated bit line sense amplifier (11), a normal I/O line (52) for receiving data from a normal bit line sense amplifier (12), a selection circuit (50) connected to the I/O lines (51,52) to connect one of the I/O lines (51,52) with a data bus sense amplifier (15), pass transisters (M51,M52) for connecting the duplicated I/O lines (51) with the data bus sense amplifier (15), a pass transisters (M53,M54) for connecting the normal I/O line (52) with the data bus sense amplifier (15), and an inverter (G5) for inverting output signal of a repair sensing circuit (10).
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