| 摘要 |
A serial-to-parallel converter circuit includes a reduced number of gate circuits necessary to configure the circuit. In the converter, each of the register blocks is constituted with an R-S flip-flop circuit including two NAND gates and an NAND gate to select the flip-flop circuit. A decoder selects one of the register blocks according to an accumulation value of serial clocks received by a counter, thereby setting data received via a data input terminal to the selected register block.
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