发明名称 |
Input EDS protection circuit |
摘要 |
The input ESD protection circuit of the present invention uses a series n+ active area resistor placed in an n-well placed in series with shunt transistor all of which are in parallel with an SCR shunt to ground circuit, thereby providing greater than +/-7000V HBM (the Mil. Std. human body model (HBM) test model) and +/-600V MM EIAJ (the EIAJ machine model (MM) test model) ESD protection response. The series n+ active area resistor is placed inside an n-well as are all metal contacts to the input, to improve junction integrity during an ESD event. The parallel SCR circuit is designed in a layout that has an n+ diffusion area tied to VSS surrounding the n+/p+ diffusion inside the n-well on three sides to provide greater surface area for current distribution.
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申请公布号 |
US5336908(A) |
申请公布日期 |
1994.08.09 |
申请号 |
US19930116100 |
申请日期 |
1993.09.02 |
申请人 |
MICRON SEMICONDUCTOR, INC. |
发明人 |
ROBERTS, GREGORY N. |
分类号 |
H01L27/02;(IPC1-7):H01L27/04;H01L29/08;H01L29/52 |
主分类号 |
H01L27/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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