| 摘要 |
PURPOSE: To enable exact control by reducing dependency on processing parameters, layout features and temperatures by operating a reset means so as to generate a reset signal under a signal coupling a sync signal, source signal and reference signal. CONSTITUTION: A phase locked loop(PLL) 10 is functioned so as to make the frequency of signal impressed to an input 22 coincident with the reference signal of input 20. A charge pump 14 is composed of a current source 32 and a current sync 34 and under the control of phase discriminator 18, a suitable control voltage is outputted through the capacitance of filter 16 to a VCO. The output of VCO 12 is impressed through a frequency divider 30 to the input 22. On the other hand, the output of stabilized oscillator 26 applies the reference signal through a frequency divider 28. When the source 32 and the sync 34 are turned on, a stabilized control signal is outputted from an AND gate 56 so as to suitably reset D type FF 52 and 54 of phase discriminator 18. A signal for operating the gate 56 is provided through a crystal oscillator 26 and the frequency divider 26. |
