发明名称 INTEGRATED CIRCUIT FOR SIGNAL PROCESSING
摘要 PURPOSE: To maintain total propagation delay within a prescribed range by composing a signal path for an integrated circuit of series-connected 1st and 2nd circuits, introducing the propagation delay to be lowered in the generation of high circuit processing speed on circuit conditions for the 1st circuit and introducing the propagation delay to be increased on the same circuit conditions for the 2nd circuit. CONSTITUTION: A private branch exchange is provided with the interface of bidirectionally operable line card 20 positioned between a telephone set 22 and a system bus 24. In one direction, an analog signal from a telephone set 26 on the line 22 is received, this is digitized and the pulse code modulated packet of data is outputted to the bus 24. In the other direction, a data packet is received from the bus 24, and an analog signal is outputted to a telephone set 26' on a line 22'. Thus, a master clock signal is supplied from a control computer, which is not shown in Figure, connected to the bus 24 to the bus 24 so that read with the specified line card can be determined.
申请公布号 JPH06216750(A) 申请公布日期 1994.08.05
申请号 JP19930253680 申请日期 1993.09.17
申请人 AMERICAN TELEPH & TELEGR CO <ATT> 发明人 JIEI EICHI FUITSUSHIYAA
分类号 H03K5/13;H03K17/04;H03K17/14;H03K17/687;H03K19/003;H03K19/0175 主分类号 H03K5/13
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