发明名称 MEMORY READOUT CIRCUIT FOR PRECHARGING AND BALANCING BEFORE READOUT
摘要 <p>PURPOSE: To make a satisfactory compromise between a reading speed and the reliability of read information by inserting a follower amplifier between the output of a differential amplifier and the drain of a precharge transistor(Tr), and inserting an additional Tr between a precharge Tr and each drain of a copy Tr. CONSTITUTION: A follower amplifier AS is connected with an output S of a differential amplifier AD, and the output is connected with the drain of a precharge TrT1 . During a precharge stage, a bit line BL and a reference line LR are turned into a potential of about 1V. The value of this potential can be controlled by the value of the voltage V1 impressed during the precharge stage. Next, during a balancing stage, the amplifier AS is made active, the charge of the line BL is changed according to the state of the output of the amplifier AD, and the output of the amplifier AD is turned to 0. Therefore, the balancing of the amplifier AD can be obtained just before a reading stage. Also, an additional TrT6 is inserted between each drain of the TrT1 and a copy Tr. Thus, a high resistance impedance can be inserted between the bit line BL and the input of the amplifier AD in a dynamic mode, and the reading speed can be increased.</p>
申请公布号 JPH06215586(A) 申请公布日期 1994.08.05
申请号 JP19930203599 申请日期 1993.07.26
申请人 SGS THOMSON MICROELECTRON SA 发明人 JIYANNMARII GOOTEIE;EMIRIO MIGERU IERO
分类号 G11C11/41;G11C11/409;G11C16/06;G11C16/26;G11C16/28;G11C17/00;(IPC1-7):G11C16/06 主分类号 G11C11/41
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