| 摘要 |
<p>PURPOSE:To enlarge the margin in drain disturbance resistance, to improve program efficiency and to accelerate the erasure by dispersing and holding whether refreshing is ended or not instead of a refresh counter at every refresh block. CONSTITUTION:A storage is constituted of a memory cell array 1 with 4M bits, a flag cell array 2, an address buffer 3, a refresh control circuit 4, an 8 bits latch circuit 5 and an address register AR. The memory cell array 1 consists of 1024 pieces of en bloc erasure blocks EB, and selects one among the en bloc erasure blocks with upper 10 bits among 19 bits of address MA, and selects 8 pieces among the memory cells in the en bloc erasure block with lower bits. The array 2 has 1024 bits of nonvolatile flag cell. The latch circuit 5 reads out the data of the memory cell in the array 1 under the control of the circuit 4 to store it temporarily at a refreshing time. The address register AR stores an address used for a refreshing time temporarily.</p> |
