| 摘要 |
PURPOSE:To send data accurately even when a delay or the like takes place by giving information for a transmission delay to a common phase signal and a common clock signal and informing the result on a receiver side, allowing the receiver side to reproduce parallel data from the signals and giving retiming to the parallel data. CONSTITUTION:A clock supply circuit section 3 generates a common phase signal 4 and a common clock 5 and supplies them to a transmission circuit section 1 and a reception circuit section 2. The transmission circuit section 1 uses a frequency divider circuit 11 to perform 1/N frequency division to the common clock 5 based on the common phase signal 4 and a processing circuit 6 processes the low speed data signal in N-parallel by using a 1/N clock as a timing signal. Furthermore, a parallel serial conversion circuit 8 applies N:1 parallel serial conversion to N-sets of low speed parallel data signal based on the common clock, and the transmission circuit section 1 sends data to the reception circuit section 2 based on the common phase signal and the common clock signal. The reception circuit section 2 reproduces the parallel data based on the sent phase signal and clock signal and conduct retiming the parallel data by using 1/N clock being an output of a frequency divider circuit 20. |
