| 摘要 |
<p>A programmable logic device having macrocells (53, 40, 55) enables gate cascades between macrocells (51, 56) to occur with a faster signal transit time, while preserving the flip flop function of the cascaded macrocells by reallocating a redirectable flip flop reset product term (42) to the flip flop (47) input. All gate product terms are retained during cascading. The macrocell logic is optimized for fast signal transit with selectable flip flop clocking. Multiplex clocking (64) and programming (CB1, CB2, CB3) are done with fewer transistors in the signal path, further reducing signal transit time.</p> |
