发明名称 Microcomputer using specific instruction bit and mode switch signal for distinguishing and executing different groups of instructions in plural operating modes
摘要 To increase the kinds of executable instructions of a microcomputer without increasing the number of bits (e.g. 8 bits) constituting one word or instruction, that is, without decreasing the execution speed or increasing the ROM usage, two or more instruction groups including instructions of different kinds, respectively, are provided operation modes are determined for the respective instruction groups; and the respective instruction groups to be executed are switched according to the respective operation modes. The microcomputer includes an instruction register, an execution control unit, a mode memory flip-flop, gates, two predecoders, a programmable logic array, an arithmetic logic unit, etc. The ordinary and special instruction groups can be selected in response to an interrupt entry signal and an interrupt return signal and a specific bit of an instruction, for instance.
申请公布号 US5335331(A) 申请公布日期 1994.08.02
申请号 US19910728681 申请日期 1991.07.12
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 MURAO, YUTAKA;WADA, TETSURO
分类号 G06F9/30;G06F9/26;G06F9/318;G06F9/32;G06F9/38;G06F15/78;(IPC1-7):G06F9/46 主分类号 G06F9/30
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