| 摘要 |
The circuit applies to image information video RAM by split transfer method. The circuit includes a clock A which has an inverted phase of RAS signal, a clock B which is in phase with SC (serial clock) signal, a clock C which makes an address of series address counter high state, a clock D and a tap loading control means which controls a tap loading of series access memory and has several inverters (1 11) , NAND gaters (1)(2), NOR gates (1-2) , and P type and N type field effect transistors. A group of 1st, 2nd, 4th, 5th, 7th, 8th, 9th,and 11th inverters is connected to an input terminals, and a group of 3th, 6th, and 10th inverters is connected to an output terminals.
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