摘要 |
An effective address pre-calculation type pipelined microprocessor comprises a register file which can be used for a base address for an operand address and an effective address calculation unit for calculating and generating an effective address of an operand prior to execution of an instruction, by using a register included in the register file as a base address register. A copy register is provided for selecting and holding either the calculated effective address or a modification amount added result obtained by adding a constant number to the calculated effective address, and a copy valid flag is provided for storing a history of a written condition of the copy register. When an auto-modification designation mode is detected, a calculated effective address or the modification amount added result is written to the copy register. A copy register identification code latch stores an identification code of a register which is used as a base address register in the auto-modification designation mode. When the copy valid flag indicates that the copy register has been written and when a value of the copy register identification code latch is consistent with a base address register number, the value of the copy register is supplied to the effective address calculation unit.
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