| 摘要 |
<p>PURPOSE:To prevent passing due to speed conversion by converting time slots again by a speed reconversion circuit to read out a highway, which is subjected to speed conversion, with an output highway read signal. CONSTITUTION:Analysis circuits (ANLA to ANLC) 1 to 3 receive indication information from software by a maintenance man, and a control timing generating circuit (CTMG) 4 generates a write or read timing required for elastic store memories(ESM) 5 and 6 based on time slot start position information from the ANLA 1, an input clock(CLK), and an input frame pulse(IFP). An input highway(IHW) is written in the ESM 5 at the timing of the start of arbitrary continuous time slots generated by the CTMG 4, and data is read out from the ESM 5 at the timing, which is a position just after the end of these time slots and is synchronized with the communication speed of an output highway (OHM), to send highway data to the ESM 6.</p> |
