| 摘要 |
PURPOSE:To reduce the number of bit operation steps and to improve an execution speed by selecting bit data in N-bit data by a bit operation circuit and rearranging the data. CONSTITUTION:The 1st selecting means 80 to 83 enter the 2nd bit data and the (2n+1)-th bit data from the 1st register 6, select required data based upon selecting information. stored in the 2nd register 7 and set up the selected data as the n-th bit data. The 2nd selecting means 84 to 87 enter the 2nd bit data and the (2n+1)-th bit data from the register 6, select required data based upon the selecting information stored in the register 7 and set up the selected data as the (n+N/2)-th bit data. The 1st selecting means 80 to 83 and the 2nd selecting means 84 to 87 input the data to the 3rd register 9. Consequently the number of bit operation steps can be reduced and the execution speed can be improved. |
