| 摘要 |
PURPOSE:To provide a semiconductor storage device which has such a NAND type DRAM structure that transistors do not exert any short-channel effect even when the transistors are integrated more closely than the pitch of word lines decided by lithography and a sufficiently large capacitor area can be secured. CONSTITUTION:In this device having a NAND type memory cell constituted by connecting in series MOS transistors and respectively connecting capacitors to the transistors, grooves 6 are formed in the memory cell forming area of an Si substrate 1 and the gates 8 of the MOS transistors are formed on the side walls of the groove 6. In addition, the source/drain diffusion layers 10 of the MOS transistors are formed on the bottoms of the grooves 6 and the surface of the substrate 1 adjacent to the grooves 6. Thereafter, after the first and second storage node electrodes 12 and 15 of the capacitors are formed in a state where they are respectively connected to the diffusion layers 10 on the bottoms of the grooves 6 and diffusion layers 10 on the surface of the substrate 1, plate electrodes 16 of the capacitors are buried so that the electrodes 16 can cover the electrodes 12 and 15. |
