| 摘要 |
The method uses a differentiated base array to form a delay circuit, simplifies a circuit design, reduces a chip size, and improves the reliability of transistor. A differentiated base array cells (21-2) has a smaller width (w) of P+ or N+ active areas (1),(3) than a basic base array cell (11) in a P channel or N channel MOS transistors (PQ1),(NQ1), and has a larger length (L) of PMOS or NMOS polygates (2a,2b),(4a,4b) than a basic base array cell (11) in a P channel or N channel MOS transistors (PQ1),(NQ1).
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