| 摘要 |
PURPOSE: To confirm the completeness of a system containing a programmable logic while continuing a general operation by independently controlling a supply source selecting port clock input and a readout input by a control mechanism. CONSTITUTION: When a pulse is imparted to a clock input 38, and a constituting control 20 imparts a logic low to a readout input 40 and a supplying source selecting port 24, the data is carried from the signal source 56 of a system 15 to a processed signal receiving device 58 through a programmable logic 12. A data compressing resistor(CR) 14 reads out and compresses the data generated by the output port 46 of the logic 12. The control 20 applies a logic high to the input 40 after a predetermined number of clock periods, and the input 38 imparts a pulse to supply an output signature to a signal output port 34. This output signature is compared with a predetermined right signature to determine the presence of an error. Thus, the own system of the logic 12 and other constituting elements of the system 15 can be confirmed. |
