| 摘要 |
PURPOSE:To eliminate or reduce a jitter component by substracting input data latched at the change point of an MSB from the input data latched at a zero cross point. CONSTITUTION:In a clock regenerating circuit using a PLL, a signal representing the MSB change point of the input data is outputted from an MSB change detecting part 21 to which a signal Q is inputted, and a DFF circuit 22 performs latch output to their signal Q by a system clock, and outputs it to DFF circuits 25, 26. While. a clock locked at an I pattern zero cross point is supplied to the DFF circuit 26 via a gate circuit 24 opened by a control signal SG, therefore, it is set as output to latch prescribed data from the input data at the DFF circuit 26. Since the leading edge of an MSB change point detection signal is set as a latch clock at the DFF circuit 25, the prescribed data is latched and outputted from the input data similarly. Therefore, a phase error signal not including the jitter component can be obtained by subtracting the output of the DFF circuit 25 from that of the DFF circuit 26. |
