| 摘要 |
PURPOSE:To vary the page size and to reduce the circuit scale of a TLB. CONSTITUTION:The logical addresses VA are divided into bits VA0-VA5, VA6-VA10, VA11-VA19, and VA20-VA31 in the order of higher places. Then the bits VA11-VA19 are divided into (k) bits of higher place variable length and (9-k) bits of lower place variable length (0<=k<=9) based on a page size code B. The lower (9-k+12) bits of the address VA are identical with the page offset. A higher place tag comparator 41 decides whether the bits VA0-VA5 are equal to the tags TAG0-TAG5 or not. Meanwhile a lower place tag comparator 42 decides whether the bits VA11-VA19 are equal to the tags TAG11-TAG19 or not in terms of the comparison valid bits. Then a switch circuit 43 validates only the comparison of higher (k) bits among those comparison results of the comparator 42 based on the page size code B. |
