| 摘要 |
PURPOSE: To enable linear interpolation between the unequally spaced nodes of interpolation with a small storage capacity without limiting maximum correction depth by capturing a correction signal as the deviation of amplitude at each single node of interpolation from the corresponding reference amplitude. CONSTITUTION: The amplitude of an initial value U0 is stored in addition registers 42, 44, and the difference U1 -U0 between the amplitude of interpolation at a first node and the initial value is divided by the number m. of arriving clock pulses and is stored in a register 48 as a voltage increase dU0 . After U1 has reached a predetermined number m0 of clock cycles, each clock cycle is incremented dU0 by the values in the addition registers 42, 44, and then a voltage increase dU1 , i.e., the difference U2 -U1 in interpolation between the first and second nodes, is divided by the number m1 of arriving clocks, and the result is loaded to the register 48 from a memory 50. These processes are repeated until interpolation of the final node is reached, so as to correct amplitude depth. |
