| 摘要 |
<p>PURPOSE:To shunt channels without delay by providing circuits for increasing and decreasing address values for a prescribed number and selecting a generated address, the increased address and the decreased address. CONSTITUTION:Received channel data are inputted to the terminal WD of a dual port RAM 10 and write addresses generated by clock signals obtained from a transmission line at a write control circuit 11 are supplied to the terminal WAD. On the other hand, the output terminal of a selector 12 is connected to the terminal RAD. The output of a read control circuit 12 is impressed to the first terminal of the selector 12 and is impressed respectively through an incremental circuit 14 for adding '1' to the address value of the circuit 13 output and a decremental circuit 15 for subtracting '1' from the address value of the circuit 13 output to the terminals 2 and 3. The selector 12 is controlled by a switching control circuit 16 and selects one of the addresses. Thus, the channels can be shunted without the delay accompanying read data.</p> |
