| 摘要 |
<p>PURPOSE:To provide a design method by which a delay time difference (skew) bet flip-flops to which a clock signal is supplied can be eliminated in a method for designing the arrangement and the wiring of the clock line of a semiconductor integrated circuit. CONSTITUTION:When a buffer circuit 54b for amplifying a clock signal is connected to a host buffer circuit 54a, the buffer circuit 54b is arranged in such a position that a manhattan distance between the input terminal of the buffer circuit 54b and the output terminal of the buffer circuit 54a becomes constant. Next, a leaf cell 56 is arranged in such a position that a manhattan distance between the input terminal of each leaf cell 56 to which a clock signal is supplied and the output terminal of the buffer circuit 54b becomes a constant value. The number of leaf cells 56 connected to every buffer circuit 54b is six. Thereby, all of the delay times of a clock signal from a clock signal pad 52 to each leaf cell 56 become equal.</p> |
