| 摘要 |
PURPOSE:To prevent the generation of a through current into a transistor (TR) connected immediately before a clock output and the increment of power consumption. CONSTITUTION:A signal from the clock output 107 is delayed by a delay circuit 110, the delay circuit is inputted to one input of a NAND gate 116 through an inverter 106, a p-type TR 118 is controlled by the output of the NAND gate 116, and an n-type TR 120 is controlled by a signal obtained by delaying an input signal 101 by a delay circuit 114. Similarly a clock output 108, a delay circuit 109, an inverter 105, a NAND gate 115, a p-type TR 117, a delay circuit 113, and an n-type TR 119 are driven. Consequently the generation of a through current can be prevented and the increment of power consumption can be prevented. |
