发明名称 APPARATUS AND METHOD FOR LOWERING OF POWER OF FUNCTIONAL UNIT IN INTEGRATED CIRCUIT
摘要 <p>PURPOSE: To automatically stop an on-chip function unit independently during non-usage by transmissively and independently the unique clock of the function unit as against another function unit unless the usage of the function unit is requested and starting the unique clock when the usage of the function unit is requested. CONSTITUTION: An internal bus controller 201 connected to a floating point device 202 generates a clock signal to be-supplied to the function unit. The floating point device 202 receives a signal which indicates whether or not a new floating point device instruction is in a pipeline and also indicates when the instruction ends. A microcode device 203 checks the decoded instruction, recognizes whether the floating point instruction is under execution, is completed or under preparation in its execution and automatically stops and restarts the floating point clock by the result.</p>
申请公布号 JPH06202754(A) 申请公布日期 1994.07.22
申请号 JP19930300811 申请日期 1993.11.08
申请人 INTEL CORP 发明人 YUUJIIN PII MATAA;YAAYA ESU SOTOUDEE;GUREGORII ESU MASHIYUUZU
分类号 G06F1/04;G06F1/32;G06F9/38;(IPC1-7):G06F1/04 主分类号 G06F1/04
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