| 摘要 |
PURPOSE:To provide a PLL circuit capable of quickly locking an optimum phase even if loop gain adjustment or the like is not executed. CONSTITUTION:In the PLL circuit 3 constituted of a phase error detecting means (21 to 29), a loop filter 30 and a VCO 31, the phase error detecting means adjusts (23, 24, 26, 28) the center frequency of the VCO 31 so as to include it within a previously set prescribed range by applying an offset value to fixed phase error information when the center frequency is deviated from the set range, and after setting up the center frequency within the prescribed range, adds the offset value applied at the time to phase error information detected from input data to output (21, 25, 28) the added value. |
