发明名称 MULTIPLEX PROCESSOR SYSTEM
摘要 PURPOSE:To perform the readout of count value of timer in high speed by keeping the synchronism of timer in the system, through the provision of output processing circuit of timer. CONSTITUTION:When the processing unit 1 stores new timer value to the timer circuit 12, the timer control circuit 10 sets the timer renewal suppression FF, and this output is given to the timer circuit via the OR gate 22 to stop the renewal of timer. Further, the output of FF21 is fed to other processing unit 2 ans similar operation is made. Next, the circuit 10 sets the timer set value to the communication register 20 and after that, sets it to the timer circuit 12 via the data line 201. Further, when the start of the communication between processing units is requested to the communication control circuit 11 via the signal line 106, the circuit 11 delivers request signal via the control line 108 to other processing unit 2 and delivers the timer set data to the processing unit 2 via the data line 201.
申请公布号 JPS5552169(A) 申请公布日期 1980.04.16
申请号 JP19780125549 申请日期 1978.10.11
申请人 NIPPON ELECTRIC CO 发明人 OOTAKI SABUROU
分类号 G06F11/18;G06F1/14;G06F15/16 主分类号 G06F11/18
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