| 摘要 |
A digital processor datapath comprising a plurality of bit slices (202) arranged on a chip in mirrored pairs (204), each bit slice (202) comprising a plurality of basic cells (203), wherein adjacent bit slices (202) form channelless boundaries therebetween. Each basic cell (203) comprises a plurality of device layers. The plurality of device layers are identical for each basic cell (203). A plurality of mask programmable conducting layers are formed over said device layers. The mask programmable conducting layers and the device layers are selectively interconnected, so that each basic cell (203) forms one of the electronic functions comprising multiplexing, inverting, latching, NANDing, NORing, exclusive ORing and exclusive NORing. |
