CMOS LOCOS ISOLATION FOR SELF-ALIGNED NPN BJT IN A BICMOS PROCESS

摘要

A method of fabricating BiCMOS devices, and the resultant BiCMOS devices are disclosed. According to the present invention, over-etching to the substrate (2) on the deposited polysilicon emitter (25) is prevented by providing additional oxide (22) beneath a polysilicon layer as an etch stop. Despite inclusion of an oxide to define an endpoint during patterning of an emitter, fabrication complexity is reduced by avoiding additional SAT (self-aligned transistor) masking and oxidation steps.