| 摘要 |
<p>A digital signal processing architecture (10) includes a timer to reset the processor and return to the first instruction periodically. Pipeline operation is enhanced using a double buffering system (22) which latches operands into the first stage of a double buffer as soon as they are ready, then to the second stage only when the last-ready operand is available and the computation unit (22) is ready to receive the operands. The processor communicates with an external unit via a random access memory (24) and a plurality of FIFOs each associated with a random access memory location. When the processor retrieves/writes a value from/to a random access memory location, a controller (26) refills the location from the corresponding FIFO or copies the value into the corresponding FIFO, respectively. Also included are instructions with a 'write-back' bit, 'branch from' instructions, a register addressing mode, an invisible move function, and an operand mask register.</p> |
