| 摘要 |
<p>A programmable digital delay line having N delay elements, two multiplexer connected to the output of the delay elements, and a comparator connected to the outputs of the multiplexers is disclosed. The invention teaches an apparatus and a method of delaying a signal, while reducing the number of delay elements and the number of connections to multiplexers. In a first embodiment of the invention, the delay elements are inverters or differential delay elements. In a second embodiment, the delay elements are differential delay elements. <IMAGE></p> |
