| 摘要 |
A nonvolatile semiconductor memory device comprises a row decoder circuit having first and second N-channel MOS transistors (33, 34) and first and second P-channel MOS transistors (35, 36) which correspond to each of word lines (12). One end of a source-to-drain current path of the first N-channel MOS transistor (33) is connected to the word line (12), and the other end thereof is connected to a corresponding one of output terminals of a predecoder circuit (21). One end of a source-to-drain current path of the second N-channel MOS transistor (34) is connected to the word line (12), and the other end thereof is supplied with a voltage of 0V or more in a data erase mode and is supplied with a low logical level signal in modes other than the data erase mode. A source-to-drain current path of the first P-channel MOS transistor (35) is connected in parallel to the source-to-drain current path of the first N-channel MOS transistor (33), and a source-to-drain current path of the second P-channel MOS transistor (36) is connected in parallel to the source-to-drain current path of the second N-channel MOS transistor (34). <IMAGE> |
