CMOS/ECL signal level converter

摘要

A signal level converter for converting CMOS input signal levels to ECL output signal levels includes first and second transistors having emitters connected to each other. The collector of the first transistor is directly connected to a first supply voltage potential. A first resistor is connected between the collector of the second transistor and the first supply voltage potential. The base of the second transistor is connected to a reference potential. A third transistor has a collector connected to the emitters of the first and second transistors. A second resistor is connected between the emitter of the third transistor and a second supply voltage potential. The base of the third transistor is connected to a control potential. A fourth transistor has a collector connected to the first supply voltage potential and a base connected to the collector of the second transistor. An input signal terminal is connected to the base of the first transistor, and an output signal terminal is connected to the emitter of the fourth transistor. The first resistor is a controllable resistor being controlled for having a high resistance when current flowing through the collector-to-emitter path of the third transistor flows through the collector-to-emitter path of the second transistor, and having a low resistance when that current flows through the collector-to-emitter path of the first transistor.