Asynchronous pulse converter

摘要

An improved pulse converter for converting a stream of asynchronous input pulses of undetermined duration into a stream of synchronous output pulses of standard duration. The input pulses may occur in any phase or frequency relationship to the reference with the limitation that the input pulses must not occur more frequently than one period of a reference clock plus one synchronizer input hold time and one synchronizer setup time. Additionally, the input pulses must be at least as wide as required to set an input flip-flop. The inventive asynchronous pulse converter requires only two flip-flops, a synchronizer, and a single Exclusive-OR gate, and a single reference clock.